This invention relates generally to emitter-coupled logic (ECL) circuits and more particularly, it relates to means for reducing an ECL reference supply voltage level during a standby or "power-down" mode of operation. A "power-down" mode is a feature which reduces the power consumption of a circuit when it is not active.
As is well known in the art. ECL circuits have been extensively used for high-speed logic circuits formed on integrated circuits. The conventional type of ECL circuit includes at least two transistors having separate collector circuits and a common emitter circuit in which a constant current source is connected. Such an ECL circuit 10 is illustrated in FIG. 1 of the drawings. The transistor Q1 is defined to be a switching transistor having its base connected to an input logic signal V.sub.in and its collector connected to a supply potential VCC via a collector load resistor R2. The transistor Q2 is defined to be a reference transistor having its base connected to a reference bias voltage V.sub.REF, its collector connected to the supply potential VCC via a collector load resistor R3 and its emitter connected to the emitter of the switching transistor Q1. A first emitter-follower transistor Q4 has its base and collector connected across the load resistor R2 and its emitter connected to an inverted output terminal V.sub.OUT. A second emitter-follower transistor Q5 has its base and collector connected across the load resistor R3 and its emitter connected to a non-inverted output terminal V.sub.OUT. The constant current source is formed of a transistor Q3 and a resistor R1. The transistor Q3 has its base connected to a reference supply voltage V.sub.CS of a reference generator 12, its collector connected to the common emitters of the transistors Q1 and Q2, and its emitter connected to a supply voltage source VEE via the resistor R1.
The constant current source provides the current I.sub.CS which can pass through two alternate current paths either via transistor Q1 or transistor Q2 by application of a suitable difference in potential between the respective bases thereof. This potential difference is achieved by the input logic signal V.sub.in applied to the base of the switching transistor Q1 and the reference bias voltage V.sub.REF applied to the base of the reference transistor Q2. The logic signal V.sub.in swings between a high or "1" binary logic level and a low or "0" binary logic level. The reference bias voltage V.sub.REF is selected to be midway between the high and low logic levels so that the potential difference between these two signal levels and the reference bias voltage determines which one of the transistors Q1 and Q2 the current I.sub.CS is passed through.
However, the disadvantage of this conventional ECL circuit is that the power consumption is high since the current I.sub.CS is always flowing through one of the transistors Q1 and Q2 regardless of whether the gate circuit is being used or is in the active mode of operation. Further, the emitter-follower transistors Q4 and Q5 are always conductive which consumes additional amounts of power.
It would therefore be desirable to provide a way of reducing the reference supply voltage level V.sub.CS for an ECL circuit during a standby mode so that no current I.sub.CS is drawn, thereby reducing the power consumption thereof. The present invention provides a circuit arrangement for reducing the reference supply voltage level of a reference generator for an ECL circuit during a power-down mode which includes a first switching network for disabling of the input of the reference generator and a second switching network for disabling the output of the reference generator so as to switch off a constant current source.